1. Field of the Invention
The present invention relates to semiconductor devices used for semiconductor memories and for peripheral circuits thereof, and to a manufacturing method thereof. More specifically, the present invention relates to manufacturing of a semiconductor device having an interconnection layer providing contacts with source/drain regions of a MOS (Metal Oxide Semiconductor) field effect transistor, and to a method for effectively manufacturing the same.
2. Description of the Background Art
A structure having an interconnection layer providing contacts with source/drain regions on a surface of a MOS field effect transistor has been used in various semiconductor devices such as semiconductor memories including DRAMs (Dynamic Random Access Memories) and peripheral circuits thereof.
The steps of manufacturing a conventional semiconductor device will be described with reference to FIGS. 1A to 1J, taking a memory cell portion of a DRAM as an example.
First, a field insulating film 2 is formed on a main surface of a p type semiconductor substrate 1 by a so called LOCOS (Local Oxidation of Silicon) method to isolate and insulate an active region. Thereafter, a gate insulating film 3, a polycrystalline silicon layer 4 formed by the CVD method and an insulating film 5 are formed successively on the surface of the semiconductor substrate 1. Thereafter, a resist mask 6 is formed on the surface of the insulating film 5 into a prescribed pattern by photolithography (FIG. 1A).
Thereafter, the insulating film 5, the polycrystalline silicon layer 4 and the gate insulating film 3 except those below the resist mask 6 are successively and selectively removed by etching, so as to form a gate electrode 7. Thereafter, n type impurity ions such as phosphorus or arsenic are irradiated on the entire surface of the semiconductor substrate 1, so as to provide n type impurity diffused regions 8 of low concentration, using the gate electrode 7 as a mask (FIG. 1B).
Thereafter, an insulating film 9 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 1C).
Thereafter, side wall spacers 10 are formed on both sides of the gate electrode by anisotropically etching the insulating film 9. Thereafter, n type impurity ions such as phosphorus or arsenic are irradiated on the entire surface of the semiconductor substrate 11, so as to form n type impurity regions 11 of high concentration, using the gate electrode 7 and the sidewall spacers 10 as masks (FIG. 1D).
Thereafter, a barrier metal layer 12 and a metal interconnection layer 13 are successively formed on the entire surface of the semiconductor substrate 1, and a resist mask 14 is formed by patterning (FIG. 1E). Thereafter, the metal interconnection layer 13 and the barrier metal layer 12 except those below the resist mask 14 are removed by etching. Thereafter, the resist mask 14 is removed (FIG. 1F), an interlayer insulating film 15 is formed on the entire surface of the semiconductor substrate 1, and a resist mask 16 for forming contact holes is patterned on the surface thereof (FIG. 1G). By etching the interlayer insulating film 16 in this state, contact holes 17 are formed, and then the resist mask 16 is removed (FIG. 1H).
Thereafter, a polycrystalline silicon layer 18 doped with impurities is formed by the CVD method on the entire surface of the semiconductor substrate 1, and a resist mask 19 is patterned on the surface thereof (FIG. 1I). By etching the polycrystalline silicon layer 18 in this state, patterning of interconnection is carried out, and then the resist mask 19 is removed (FIG. 1J).
In the memory cell manufactured through the above described steps, the gate electrodes 7 serve as word lines, and the metal interconnection layer 13 serves as a bit line. The polycrystalline silicon layer 18 serves as a lower electrode (storage node) of a capacitor (not shown) formed in the succeeding steps. The position of the contact portion 20 between the n type impurity diffused region 11 of high concentration and the polycrystalline silicon layer 18 is determined by patterning and etching of the resist mask 16. The width s.sub.1 and s.sub.2 of the left and right sidewall spacers 10 on the surface of the semiconductor substrate 1 are approximately the same, and only on the side of the polycrystalline silicon layer 18 an interlayer insulating film 15 having the width of s.sub.3 is provided. Accordingly, the distance between the contact portion 21 and the n type impurity diffused region 11 of high concentration is shorter than the distance between the contact portion 20 and the n type impurity diffused region 11 on the surface of the semiconductor substrate 1, by about s.sub.3. By ensuring longer distance between the contact portion 20 and the gate electrode 7 in this manner, degradation of characteristics caused by diffusion of the impurities doped in the polycrystalline silicon layer 18 to the active region is suppressed.
However, the conventional method of manufacturing the semiconductor device has the following disadvantages.
If the patterning of the resist mask 16 is out of position as shown in FIG. 2A due to patterning error during photolithography of the resist mask 16 to form the contact holes 17, the state of FIG. 2B corresponding to FIG. 1I of the prior art and then the state of FIG. 2C corresponding to FIG. 1J result. In this case, if the patterning error of the resist mask 16 exceeds s.sub.3 of FIG. 1J, the distance s.sub.4 between the contact portion 20 and the gate electrode 7 on the surface of the semiconductor substrate 1 becomes shorter than s.sub.2 shown in FIG. 1J, as shown in FIG. 2C. Since the distance s.sub.4 is shorter than the distance s.sub.1 between the contact portion 21 and the gate electrode 7, degradation of characteristics caused by diffusion of impurities doped in the polycrystalline silicon layer 18 to the active region becomes a serious problem.
More specifically, the impurities doped in the polycrystalline silicon layer 18 are diffused to the active region of the semiconductor substrate 1 to reach the n type impurity diffused region 8 of low concentration, thereby increasing the concentration thereof. Therefore, electric field releasing effect realized by moderate change in concentration of the source/drain regions near the channel region is reduced, and hence peak electric field strength is increased.
If a metal interconnection is used instead of the polycrystalline silicon layer 18, the impurities are not diffused. However, since the distance between the metal interconnection and the polysilicon layer 18 of the gate electrode 7 becomes short, insulation therebetween may be degraded, and there may possibly be a short circuit in the worst case, making the whole device defective. If the metal interconnection layer is positioned to be in contact with the surface of the n type impurity diffused region 8 of low concentration, there is a possibility of so called alloy spike, in which the metal interconnection layer piercing through the n type impurity diffused region 8 of low concentration directly reacts with the silicon in the semiconductor substrate 1. If the alloy spike is generated, insulation between the metal interconnection layer and the semiconductor substrate would be degraded.